1. Field of the Invention
The present invention relates to a microprocessor having a register bank architecture in which a built-in RAM and general-purpose registers are connected through an exclusive high-speed bus in order to that the contents of the general-purpose registers agree with the contents of the built-in RAM specified by a bank pointer, and, in particular, to a microprocessor having a register bank architecture wherein a wait time for execution of a following instruction caused during the switching operation of a bank in the register banks can be reduced.
2. Description of the Prior Art
Conventionally, in a conventional microprocessor having a register bank architecture, a built-in RAM 126 and general-purpose register group 127 are connected through a exclusive high-speed bus 128 in order to that the contents of the general-purpose register group 127 are agreed with the contents of the built-in RAM 126. In the conventional microprocessor, contents of the general-purpose register group 127 are stored and loaded to/from the RAM 126 by setting a destination part of a normal instruction with a current bank pointer (CBP). In addition, when a task change operation is performed, the data in the general registers are automatically stored and loaded through the exclusive high speed bus 128.
FIG. 1 is a configuration diagram of a conventional single-chip microprocessor 100 having a register bank architecture. FIG. 2 is a configuration diagram of a CPU core formed in this single-chip microprocessor 100 shown in FIG. 1.
As illustrated in FIG. 1, a microprocessor 100 comprises a plurality of blocks such as a CPU core 101, the built-in RAM 126, the built-in ROM 105, a bus controller 107, an interrupt controller 109, a timer 111, and a serial I/O 113, and the like mounted on one chip. These blocks transfer data through a system bus SYSBUS (containing an address bus ABUS and a data bus DBUS) in the chip. In addition, data transmission between the chip and external devices is performed through I/O pads in the chip under the control of the bus controller 107.
As illustrated in FIG. 2, this conventional technology there is the RAM 126 making up a RAM such as a Static Random Access Memory (SRAM) and the general-purpose register group 127 comprises a plurality of register banks in the CPU core 101. The RAM 126 is connected to the internal bus including IDBUS1 to IDBUS3 in the CPU core 101. Data is transferred through the internal bus of IDBUS1 to IDBUS3 to an ALU 125 (Arithmetic Logic Unit) where operations are performed.
FIG. 3 is a general configuration diagram of explaining a conventional register bank architecture in the general-purpose register group 127 builded-in the conventional microprocessor core 101 shown in FIG. 2. FIG. 4 is a configuration diagram of a conventional bank control unit BCU. FIG. 5 is a timing chart for explaining a bank switching operation in the register banks in the general-purpose registers 126.
An instruction decoder 121 decodes an instruction word transmitted from a bus interface unit (omitted from FIG. 2), reads out a microcode, and generates a control signal for controlling each block. When the microcode which provides destination operand data indicates a Current Bank Pointer (CBP), a Current Bank Pointer accumulation Control signal (CBPC) is switched to an enable level (to a High Level shown in FIG. 5). The bank control unit BCU which has received the current bank pointer accumulation control signal CBPC generates a bank stop signal STOP to each block in order to inform that the register banks 127 is now used, so that the blocks which have received the stop signal STOP do not process the next instruction.
For example, as shown in FIG. 3, in the general-purpose register group 127 (R0 to R15) made up of sixteen 16-bit registers, these registers are groped into four register banks RF1 to RF4 in which the general-purpose registers R0 to R3 are grouped as first register bank RF1, the general-purpose registers R4 to R7 as second register bank RF2, the general-purpose registers R8 to R11 as third register bank RF3, and the general-purpose registers R12 to R15 as fourth register bank RF4. In this case, data is transferred between the general-purpose register group 127 and the built-in RAM 126 per register bank at a time through the high-speed 64-bit bus 128.
The store/load operations for the general-purpose register group 127 (R0 to R15) will now be explained with reference to the timing chart shown in FIG. 5.
Data in the general-purpose register group (GR) 127 from the first register bank RF1 to the fourth register bank RF4 is transmitted in sequence to the region of the 8-byte in the built-in RAM 126 from an address indicated by the current bank pointer CBP because one bank has 8 bytes (hereinafter abbreviated to cbp.times.8).
A register address REGA transmitted from the Bank control Unit BCU to the general-purpose register group 127 is designated by four bits corresponds to a register number, for example, the number "0" in the register R0. The time for one clock signal is required to transfer one bank between the general-purpose register group 127 and the RAM 126.
The contents of each of the first register bank RF1, the second register bank RF2, the third register bank RF3, and the fourth register bank RF4 are transmitted to the regions in the built-in RAM 126, the regions are addressed by cbp.times.8bytes, (cbp+1).times.8 bytes, (cbp+2).times.8 bytes, and (cbp+3).times.8 bytes, respectively.
The bank control unit BCU receives a current bank pointer write-in request signal CBPW during the cycle in which the transmission from the general-purpose register group 127 to the built-in RAM 126 completes, and data designating a new current bank pointer is transmitted to the current bank pointer CBP from a data register (omitted from FIG. 3) through a internal bus IBUS.
In the next cycle, the contents of an 8-byte (cbp'.times.8) RAM region are transmitted to the first register bank RF1 from an address cbp' in the RAM 126 indicated by the current bank pointer CBP.
Transmission is performed in the same manner for the second register bank RF2 to the fourth register bank RF4. Then, the bank stop signal STOP is disabled and the transmission termination is communicated to each block simultaneously in the transmission cycle for the fourth register bank RF4.
Specifically, the execution of the instruction is in a standby state for at least eight clock signals required for transmission during bank switching, regulated by the bank stop signal STOP.
As outlined in the foregoing description, with a conventional microprocessor, the number of general-purpose registers or register banks stored and loaded is fixed, and a method is adopted whereby all of the register banks RF1 to RF4 in the general-purpose register group 127 are transferred to/from the build-in RAM 126 in one transmission operation. Therefore the number of clock cycles required for storing and loading the contents of the general-purpose register group 127 is determined by the number of general-purpose registers and which is also determined by the bit width of the exclusive high-speed bus 128 through which the RAM 126 and the general-purpose register group 127 are connected.
However, when four general-purpose registers make up one bank and there are 16 general-purpose registers, eight clock cycles must be required, for example, merely for storing and loading for all of the register banks RF1 to RF4.
Because the execution of the next instruction must wait during this interval, there is the problem that the efficiency of execution of the instructions drops.